Reductions in the sizes of semiconductor devices (for example, Metal-Oxide-Semiconductor (MOS) devices) have enabled continued improvements in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of a transistor, modulating the length of the channel region underlying the gate between the source and drain of a MOS device alters a resistance associated with the channel region, thereby affecting the performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which, assuming all other parameters are maintained relatively constant, may allow an increase in the current flow between the source and the drain when a sufficient voltage is applied to the gate of the transistor.
To further enhance the performance of MOS devices, stress may be introduced into the channel region of a MOS device to improve its carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (NMOS) device in a source-to-drain direction and to induce a compressive stress in the channel region of a p-type MOS (PMOS) device in a source-to-drain direction.
A commonly used method for applying compressive stresses to the channel regions of PMOS devices is to grow SiGe stressors in the respective source and drain regions. Such a method typically includes the steps of forming a gate stack on a semiconductor substrate, forming spacers on sidewalls of the gate stack, forming recesses in the silicon substrate along the gate spacers, epitaxially growing SiGe stressors in the recesses, and then annealing the substrate. SiGe stressors apply a compressive stress to the channel region, which is located between the source SiGe stressor and the drain SiGe stressor. Similarly, for NMOS devices, stressors that may introduce tensile stresses, such as SiC stressors, may be formed.